Physical Design Engineer

Responsibilities

• Own ASIC physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and optimization.
• Drive timing closure and signoff across all modes and corners (MCMM).
• Resolve DRC/LVS, congestion, signal integrity, IR drop, and EM issues.
• Collaborate with RTL, STA, DFT, Analog, and Packaging teams.

Requirements

• Degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or related field.
• Strong hands-on experience in full-chip or block-level physical design.
• Expertise in timing closure, physical verification, power optimization, and signoff.
• Experience with advanced technology nodes and MCMM flows.
• Familiarity with Synopsys ICC2/Fusion Compiler or Cadence Innovus.
• Knowledge of IR drop, EM, and power integrity analysis.
• Experience with Intel design flow and ≤7nm technologies is an advantage.