Responsibilities

• Define and implement DFT architecture for SoCs and subsystems.
• Develop and verify Scan, MBIST, LBIST, and Boundary Scan structures.
• Perform scan insertion, ATPG, and fault simulation.
• Analyze and improve test coverage for manufacturing defects.
• Debug DFT and ATPG issues during simulation and silicon validation.

Key Requirements

• Strong knowledge of digital design and VLSI fundamentals.
• Hands-on experience in DFT methodologies, including Scan, ATPG, fault models, and test compression.
• Familiarity with industry-standard DFT tools such as Synopsys DFT Compiler/TestMAX, Cadence Modus, or Siemens Tessent.
• Scripting skills in TCL, Python, or Perl are an advantage.